In general, the present invention relates to data recovery in phase-locked loop (PLL)-type circuits as well as the use of PLLs for generating, aligning, and recovering data such as clock signals. More particularly, this invention relates to: an improved circuit for detecting whether a reference clock signal of a PLL is aligned with incoming data; an improved PLL circuit for recovering a clock signal from incoming data; and an improved method for recovering data in a PLL.
Background information describing and illustrating PLLs currently in use for clock generation and synchronization can be found in an 1992 IEEE publication Circuit & Devices article entitled Designing On-Chip Clock Generators (pp. 32-36), authored by applicant Dr. Dao-Long Chen, as well as two reference texts: Electronic Communication Techniques, third edition, by Paul H. Young (see esp. all of chapter 10, and pp. 721-723); and Principles of CMOS VLSI Design, A Systems Perspective, second edition, by Neil H. E. Weste and Kamran Eshraghian (see esp. pp. 334-336, and pp. 685-689).
PLL data recovery circuits are useful for recovering data and/or clock signals after transmission over a distance using, for example, fiber-optic (glass) cables. One recent PLL-type combination clock recovery circuit and demultiplexer circuit has been described (U.S. Pat. No. 5,301,196) to operate at either half, or one-quarter, the data rate of a received data signal. The combination of circuits described is preferably designed for "the logic family . . . [of] Gallium Arsenide (GaAs) MESFET differential current switched logic". The circuit combination includes a ring oscillator for generating either two phase-shifted clocks (0.degree. and 90.degree. for the half-speed circuit), or four phase-shifted clocks (0.degree., 45.degree., 90.degree., and 135.degree. for the one-quarter speed circuit). The received data signal is used to edge-trigger either two (in the half-speed circuit), or four (in the one-quarter speed circuit) flip-flops to sample, respectively, either the two clocks (0.degree. and 90.degree.), or four clocks (0.degree., 45.degree., 90.degree., and 135.degree.). The outputs of either the two, or four, flip-flops are then fed into an exclusive-OR gate, or a parity generator which has been connected in series with a loop filter and the ring oscillator.
PLL circuits used in today's high frequency systems are typically made using Silicon (Si) bipolar or GaAs (as preferred in the half- and quarter-speed circuits described above) integrated circuit technology. These PLL technologies are very limited in use--either due to high power consumption or high manufacturing cost. It is well understood that the manufacturing cost and/or power dissipation in MOS is generally lower than in comparable Si bipolar or GaAs circuits. These, among other reasons, make it desirable to build PLLs for high-performance communications systems using CMOS technology. However, building PLL components out of CMOS that can reliably operate at such very high data rates (for example, at or in excess of 1-Gb/sec), has been beyond current CMOS technology capabilities. The new PLL circuits and new method described herein make it possible to use current CMOS fabrication technology (although not limited thereto) to build PLL circuits for clock generation, alignment with incoming data, and recovery, as well as for data sampling and recovery.